Traditionally, integrated circuits are formed on semiconductor chips. In order to interconnect these chips with other components of an integrated electronic device, the chips are wire bonded into a package which includes a number of signal pins. The package is then bonded onto a printed circuit board (PC board). The pins on each of the packages are connected using strips of metal bonded to the surface of the PC board which is typically formed of a sheet of fiberglass or similar insulating material.
Packages for chips degrade intrinsic chip performance and add cost and space. Alternatively, bare chips may be bonded on top of a piece of silicon bearing an interconnect system directly, either with flip-chip or wirebond technology. The interconnects between chips are formed in this semiconductor substrate using conventional photolithographic techniques. In addition, multiple layers of interconnects can be formed on the substrate using standard semiconductor processing techniques. The interconnecting nets are coupled to the chips through either small bumps of solder, or wire bond pads which are referred to as nodes. The chips to be bonded to the substrate have corresponding nodes on their surface. The chips to be bonded may then be "flipped" or wire bonded onto the substrate and the corresponding nodes are bonded together. This allows for greater device density because of the smaller geometries possible using semiconductor process techniques to form the interconnects.
In order to get good assembly yield it is extremely important to determine if the interconnecting nets have been properly formed in the substrate prior to bonding. The interconnecting nets must be tested to ensure continuity between each of the nodes in the net. Each of the nets must also be tested for erroneous connections to other nets.
Traditional PC boards are tested using bed-of-nails testers. This method of testing is impractical for silicon-on-silicon multi-chip technology because of the extremely small geometries involved. It is physically impossible to build a bed-of-nails tester which is capable of testing the thousands of points in the interconnecting nets spaced microns apart.
Accordingly, a need has arisen for a system and method for testing the interconnecting nets formed in the substrates prior to the bonding of the chips on the substrates. The method and system must test for continuity within the nets as well as for erroneous connections between the nets.